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SH7052 bảng dữ liệu(PDF) 376 Page - Renesas Technology Corp

tên linh kiện SH7052
Giải thích chi tiết về linh kiện  SuperHTM RISC engine
PDF  919 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7052 bảng dữ liệu(HTML) 376 Page - Renesas Technology Corp

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after setting H'FFFF in the cycle register, the cycle register’s compare-match flag and overflow
flag will be set simultaneously.
Note that 0% or 100% duty output is not possible in channel 3 to 5 PWM mode.
An example of channel 3 to 5 PWM mode operation is shown in figure 10.23.
In the example in figure 10.23, H'F0008 is set in GR3D, H'0002 is set in GR3A, GR3B, and
GR3C, and channel 3 is activated; then, during operation, H'0000 is set in GR3A, GR3B, and
GR3C, and output is performed to external pins TIOA3 to TIOC3. Note that 0% duty output is not
possible even though H'0000 is set.
Pø
TCNT3
Clock
TCNT3
GR3D
GR3A–3C
(pulse width)
TSR3
TIO3A–
TIO3C
0000
Cleared by software
0005
0004
0003
0002
0001
0000
0008
0007
0003
0002
0008
0000
0001
0002
0008
0008
Cleared by software
Rewritten by software
Figure 10.23 Channel 3 to 5 PWM Mode Operation
10.3.11
Event Count Function and Event Cycle Measurement
Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and corresponding general registers
(GR9A to GR9F). Each event counter has an external pin (TI9A to TI9F).
Each ECNT9 operates unconditionally as an event counter. When an edge is input from the
external pin, ECNT9 is incremented. When ECNT9 matches the value set in GR9, it is cleared,
and then counts up when an edge is again input at the external pin. By making the appropriate
setting in the interrupt enable register (TIER) beforehand, an interrupt request can be sent to the
CPU on compare-match.
For ECNT9A to ECNT9D, a trigger can be transmitted to channel 3 when a compare-match
occurs. In channel 3, if the channel 9 trigger input is set in the timer I/O control register (TIOR)
and the corresponding bit is set to 1 in the timer start register (TSTR), the TCNT3 value is
captured in the corresponding general register (GR3A to GR3D) when an ECNT9A to ECNT9D
compare-match occurs. This enables the event cycle to be measured.



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