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SH7052 bảng dữ liệu(PDF) 372 Page - Renesas Technology Corp

tên linh kiện SH7052
Giải thích chi tiết về linh kiện  SuperHTM RISC engine
PDF  919 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7052 bảng dữ liệu(HTML) 372 Page - Renesas Technology Corp

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register (TSR0) is set. There are four interrupt sources for the respective ITVRR registers, but
there is only one interrupt vector.
To suppress interrupts and A/D converter activation, ITVRR bits should be cleared to 0.
An example of interval timer function operation is shown in figure 10.19.
In the example in figure 10.19, TCNT0 is started by setting ITVE to 1 in ITVRR1.
Pø
TCNT0
Clock
Internal
detection
signal
AD
activation
trigger
TCNT0
In case of bit 6 detection
In case of bit 7 detection
0000007E
00000085
00000084
00000083
00000082
00000081
00000080
0000007F
00000040
0000003F
0000003E
0000003D
0000003C
Figure 10.19 Interval Timer Function
10.3.8
Twin-Capture Function
Channel 0 input capture register ICR0A, channel 1 offset base register 1 (OSBR1), and channel 2
offset base register 2 (OSBR2) can be made to perform input capture in response to the same
trigger by means of a setting in timer I/O control register 0 (TIOR0).
When TCNT0, TCNT1A, and TCNT2A in channel 0, channel 1, and channel 2 are started by a
setting in the timer status register (TSR), and an edge is input to ICR0A, the TCNT1A value is
transferred to OSBR1, and the TCNT2A value to OSBR2. Edge detection is as described in
section 10.3.4, Input Capture Function.
An example of twin-capture operation is shown in figure 10.20.



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