SH7052 datasheet(375/919 Pages) RENESAS

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349

Pø

Cycle

Duty = 100%

Cycle

Duty = 0%

Cycle

Data = 0003

Data = 0004

Data = 0000

Down

No PWM output for 1

cycle after activation

TST6A

TCNT6A

Clock

TCNT6A

up-/down-

count

TCNT6A

CYLR6A

Write to

BFR6A

DTR6A

TO6A

TSR6

0004

0002

0003

0004

0000

Cleared by software

Figure 10.22 Complementary PWM Mode Operation

10.3.10

Channel 3 to 5 PWM Function

PWM mode is selected for channels 3 to 5 by setting the corresponding bits to 1 in the timer mode

In PWM mode, general registers D (GR3D, GR4D, GR5D) are used as cycle registers, and general

registers A to C (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) as duty registers. The

external pins (TIO3A to TIO3C, TIO4A to TIO4C, TIO5A to TIO5C) corresponding to the GRs

used as duty registers are used as PWM outputs. External pins TIO3D, TIO4D, and TIO5D should

not be used as timer outputs.

The free-running counter (TCNT) is started by making a setting in the timer start register (TSTR),

and when TCNT reaches the cycle register (GR3D, GR4D, GR5D) value, a compare-match is

generated and TCNT starts counting up again from H'0000. At the same time, the corresponding

bit is set in the timer status register (TSR) and 1 is output from the corresponding external pin.

When TCNT reaches the duty register (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) value,

0 is output to the external pin. The corresponding status flag is not set. When PWM operation is

performed by starting the free-running counter from its initial value of H'0000, PWM output is not

performed for one cycle. To perform immediate PWM output, the value in the cycle register must

be set in the free-running counter before the counter is started. If PWM operation is performed

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