SH7021 datasheet(113/509 Pages) RENESAS

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8.1.3

Pin Configuration

Table 8.1 shows the BSC pin configuration.

Table 8.1

Pin Configuration

Name

Abbreviation

I/O

Function

Chip select 7–0

CS7–CS0

Chip select signal that indicates the area being

accessed

Read

Strobe signal that indicates the read cycle

High write

WRH

Strobe signal that indicates write cycle to upper 8 bits

Low write

WRL

Strobe signal that indicates write cycle to lower 8 bits

Write

WR*1

Strobe signal that indicates write cycle

High byte strobe

HBS*2

Strobe signal that indicates access to upper 8 bits

Low byte strobe

LBS*3

Strobe signal that indicates access to lower 8 bits

Row address strobe

RAS

DRAM row address strobe signal

High column

address strobe

CASH

Column address strobe signal for accessing the

upper 8 bits of the DRAM

Low column address

strobe

CASL

Column address strobe signal for accessing the lower

8 bits of the DRAM

Address hold

Signal for holding the address for address/data

multiplexing

Wait

WAIT

Wait state request signal

Address bus

A21–A0

Address output

Data bus

AD15–AD0

I/O

Data I/O. During address/data multiplexing, address

output and data input/output.

Data bus parity high

DPH

I/O

Parity data I/O for upper byte

Data bus parity low

DPL

I/O

Parity data I/O for lower byte

Notes: 1. Doubles with the WRL pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus

Control Register, for details.

2. Doubles with the A0 pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus

Control Register, for details.

3. Doubles with the WRH pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus

Control Register, for details.

8.1.4

The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM

interface, and parity check.

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