SH7021 datasheet(99/509 Pages) RENESAS

tên linh kiện	SH7021

Giải thích chi tiết về linh kiện	SuperH??RISC engine

PDF	509 Pages

Scroll/Zoom	100%

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Bit:

Bit name:

—

Initial value:

R/W:

—

Bit:

Bit name:

CD1

CD0

ID1

ID0

RW1

RW0

SZ1

SZ0

Initial value:

R/W:

R/W

•

Bits 15–8 (reserved): These bits always read as 0. The write value should always be 0.

•

Bits 7 and 6 (CPU cycle/DMA cycle select (CD1 and CD0)): CD1 and CD0 select whether to

break on CPU and/or DMA bus cycles.

Bit 7: CD1

Bit 6: CD0

Description

No break interrupt occurs (initial value)

Break only on CPU cycles

Break only on DMA cycles

Break on both CPU and DMA cycles

•

Bits 5 and 4 (instruction fetch/data access select (ID1, ID0)): ID1, ID0 select whether to break

on instruction fetch and/or data access bus cycles.

Bit 5: ID1

Bit 4: ID0

Description

No break interrupt occurs (initial value)

Break only on instruction fetch cycles

Break only on data access cycles

Break on both instruction fetch and data access cycles

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