7643 datasheet(312/424 Pages) RENESAS

312 / 424 page

Rev.2.00

Aug 28, 2006

page 191 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.10 Clock generating circuit

Fig. 2.10.4 Structure of Frequency synthesizer control register

Frequency synthesizer control register

b7 b6 b5 b4 b3 b2 b1 b0

Frequency synthesizer control register

(FSC : address 6C16)

Name

Functions

At reset R W

Frequency synthesizer

input bit (FIN)

LPF current control bit

(CHG1, CHG0) (Note)

0 : Disabled

1 : Enabled

0 : f(XIN)

1 : f(XCIN)

Frequency synthesizer

lock status bit

0 : Unlocked

1 : Locked

Frequency synthesizer

enable bit (FSE)

Nothing is arranged for this bit.

Fix this bit to “0”.

Nothing is arranged for these bits.

Fix these bits to “0”.

b1b0

0 0 : Not available

0 1 : Low current

1 0 : Intermediate current (recommended)

1 1 : High current

Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset.

When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after

locking the frequency synthesizer.

Frequency synthesizer multiply register 1

b7 b6 b5 b4 b3 b2 b1 b0

Frequency synthesizer multiply register 1

(FSM1: address 6D16)

Functions

At reset R W

qfVCO clock is generated by multiplying fPIN clock, which is generated

by FSM2, by the contents of this register:

fVCO = fPIN • {2(n +1)}, n: value set to FSM1.

Fig. 2.10.5 Structure of Frequency synthesizer multiply register 1

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