7643 datasheet(292/424 Pages) RENESAS

292 / 424 page

Rev.2.00

Aug 28, 2006

page 171 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.7 PLL

2.7.3 Functional description

The frequency synthesizer generates the 48 MHz clock required by fUSB and fSYN, which are multiples of

the external input reference f(XIN) or f(XCIN). To use the frequency synthesizer, set the frequency synthesizer

enable bit of frequency synthesizer control register (address 6C16) to “1”.

The frequency synthesizer input bit selects either f(XIN) or f(XCIN) as an input clock fIN for the frequency

synthesizer.

Figure 2.7.7 shows the block diagram for the frequency synthesizer circuit.

(1) fPIN

fIN is divided by the contents of frequency synthesizer multiply register 2 (FSM2: address 6E16) to

generate fPIN, where

fPIN = fIN / 2(n + 1), n: value set to FSM2.

When the value of FSM2 is set to 255, the division is not performed and fPIN will equal fIN.

Figure 2.7.8 shows the frequency synthesizer multiply register 2 setting example.

Note: Be sure to set fPIN to 1 MHz or more.

FSM2

Data Bus

FSM1

FSC

Prescaler

fIN

fPIN

fVCO

fSYN

fUSB

(address 006E16)

(address 006D16)(address 006C16)(address 006F16)

FSD

Frequency

Multiplier

Frequency Divider

Fig. 2.7.7 Block diagram for frequency synthesizer circuit

24 MHz

1 MHz

2 MHz

3 MHz

6 MHz

12 MHz

Decimal

255

Hexadecimal

FF16

24.00 MHz

fIN

24.00 MHz

0B16

0516

0316

0116

0016

fPIN

FSM2 register set value

Fig. 2.7.8 Frequency synthesizer multiply register 2 setting example

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