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7643 bảng dữ liệu(PDF) 241 Page - Renesas Technology Corp |
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7643 bảng dữ liệu(HTML) 241 Page - Renesas Technology Corp |
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241 / 424 page ![]() Rev.2.00 Aug 28, 2006 page 120 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.6 USB Fig. 2.6.18 Structure of USB endpoint x (x=0 to 2) OUT write count register USB endpoint x OUT write count register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x (x=0 to 2) OUT write count register (WRT_CNT : address 5D16) b 0 1 2 4 Name 0 Functions At reset R W 0 0 0 0 5 0 6 7 0 0 3 Contains the number of bytes in endpoint x OUT FIFO. ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ (12) USB endpoint x (x = 0 to 2) OUT write count register This is an 8-bit register that contains the number of bytes in the endpoint x (x = 0 to 2) OUT FIFO. This register must be read after the USB FCU has received a packet of data from the host CPU. Refer to this register when reading the data from the OUT FIFO. When there are two packets in the FIFO (double-buffer), the number of bytes of data in the first packet received will be read out from the register. After one packet of data is read from the FIFO and the OUT_PKT_RDY flag is cleared, the value of the register will be updated to the number of bytes of the packet received last. Figure 2.6.18 shows the structure of the USB endpoint x (x = 0 to 2) OUT write count register. |
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