7643 datasheet(227/424 Pages) RENESAS

227 / 424 page

Rev.2.00

Aug 28, 2006

page 106 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.6 USB

Fig. 2.6.9 Structure of USB power management register

USB power management register

b7 b6 b5 b4 b3 b2 b1 b0

USB power management register

(USBPM : address 5116)

Name

Functions

At reset R W

USB resume detection flag

(RESUME)

0 : No USB suspend detected

1 : USB suspend detected (Note 1)

0 : No USB resume signal detected

1 : USB resume signal detected

USB suspend detection

flag (SUSPEND)

Nothing arranged for these bits. Fix these bits to

0 : End of remote resume signal

1 : Transmitting of remote resume signal

(only when SUSPEND = “1”) (Note 2)

USB remote wake-up bit

(WAKEUP)

Notes 1: This bit is cleared when the WAKEUP bit is “1”.

2: When the SUSPEND bit is “1”, set this bit to “1” and keep “1” for 10 ms to 15 ms.

(3)

USB power management register

This register is used for power management in the USB FCU.

q USB suspend detection flag

If no activity is detected on the D+/D- line for a period of 3ms, this flag is set to “1” and a USB

suspend interrupt occurs.

When the USB resume detection flag is set to “1” after the MCU returns from the USB suspend

state by a USB resume interrupt, the USB suspend detection flag is automatically cleared to “0”.

Even if the USB remote wake-up bit is cleared to “0” after the MCU returns from the suspend

state by a remote wake-up (USB remote wake-up bit set to “1”), the suspend detection flag is

not automatically cleared to “0”. Clear this flag to “0” by software.

q USB resume detection flag

When a non-idle signal is detected on the D+/D- line in the suspend mode, this flag is set to

“1” and a USB resume interrupt occurs. This flag is cleared to “0” when the USB resume signal

interrupt status flag of USB interrupt status register 2 is cleared to “0”.

q USB remote wake-up bit

Set this bit to “1” after the MCU returns from the USB suspend state by a remote wake-up (INT

interrupt, etc.). While this bit is “1”, the USB FCU sends a resume signal to the host CPU,

informing it of the return from the suspend state. Clear the bit to “0” after holding it at “1” for

10ms to 15ms.

Figure 2.6.9 shows the structure of the USB power management register.

7643 bảng dữ liệu(PDF) 227 Page - Renesas Technology Corp

7643 bảng dữ liệu(HTML) 227 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL