7643 datasheet(192/424 Pages) RENESAS

192 / 424 page

Rev.2.00

Aug 28, 2006

page 71 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.4 UART

Initialization

8016

0016

FF16

0016

4116

101100X02

XXXX01012

000000012

X00000012

0816

0X00X0002

4D16

010X00002

010X1X102

00XXXXXX2

3416

0016

6116

0016

6416

0016

00110X0X2

1X0X00012

X0X1XXX12

XX0000002

0016

RESET

(Interrupt disabled)

(interrupt enabled)

CCR (Address : 1F16)

FSM1 (Address : 6D16)

FSM2 (Address : 6E16)

FSD (Address : 6F16)

FSC (Address : 6C16)

USBC (Address : 1316)

USBFIFOMR (Address : 5F16)

USBIE1 (Address : 5416)

USBINDEX (Address : 5816)

IN_MAXP (Address : 5B16)

IN_CSR (Address : 5916)

UBRG (Address : 3116)

UMOD (Address : 3016)

UCON (Address : 3316)

DMAIS (Address : 3F16)

DMA0SL (Address : 4216)

DMA0SH (Address : 4316)

DMA0DL (Address : 4416)

DMA0DH (Address : 4516)

DMA0CL (Address : 4616)

DMA0CH (Address : 4716)

DMA0M1 (Address : 4016)

DMA0M2 (Address : 4116)

ICONA (Address : 0516)

ICONB (Address : 0616)

IREQA (Address : 0216)

IREQB (Address : 0316)

.....

Refer to the USB initiral setting.

• USB initializing

Endpoint1FIFO : OUT128 bytes

Endpoint0, Endpoint1IN interrupt enabled

Max. packet size : 64 bytes

...

• UART initializing

φ as UART clock, 1 stop bit,

Parity checking disabled, 8-bit character length

CTS function disabled, RTS function enabled

Receive enabled

• DMA initializing

DMA0 selected

Source address : UART receive buffer

Destination address : USBFIFO1

Transmit byte : 64 bytes fixed

DMAC channel 0 source register increment : disabled

DMAC channel 0 destination register increment : disabled

DMAC channel 0 write control : Writing data in reload latch only

DMAC count register underflow : enabled

DMAC channel 0 transfer mode : cycle steal transfer mode

DMAC channel 0 hardware transfer request : UART receive interrupt

DMAC channel 0 : enabled

• Others

USB function interrupt : enabled

DMAC0 interrupt : enabled

UART receive buffer full interrupt : disabled

UART summing error interrupt : disabled

.....

q x: This bit is not used here. Set it to “0” or “1” arbitrarily.

Fig. 2.4.35 Control procedure (1)

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