7643 datasheet(120/424 Pages) RENESAS

120 / 424 page

Rev.2.00

Aug 28, 2006

page 103 of 103

REJ09B0133-0200

OVERVIEW

7643 Group

FUNCTIONAL DESCRIPTION SUPPLEMENT

Timing After Interrupt

The interrupt processing routine begins with the machine cycle fol-

lowing the completion of the instruction that is currently in

execution. Figure 96 shows a timing chart after an interrupt oc-

curs, and Figure 97 shows the time up to execution of the interrupt

processing routine.

Fig. 96 Timing chart after interrupt occurs

Fig. 97 Time up to execution of interrupt processing routine

PCH

PCL

S, SPS

S-2, SPS

S-1, SPS

AL, AH

Address bus

Data bus

Not used

: CPU operation code fetch cycle

(This is an internal signal which cannot be observed from the external unit.)

: Vector address of each interrupt

: Jump destination address of each interrupt

: “0016” or “0116”

SYNC

BL, BH

AL, AH

SPS

SYNC

7 to 23 cycles (f(

φ) = 12 MHz, 0.583 µs to 1.92 µs)

Interrupt request occurs

Main routine

Interrupt processing routine

2 cycles

5 cycles

Waiting time for

pipeline post-

processing

Push onto

stack vector

fetch

Interrupt operation starts

0 to 16 cycles

FUNCTIONAL DESCRIPTION SUPPLEMENT

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