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SH7014 bảng dữ liệu(PDF) 174 Page - Renesas Technology Corp

tên linh kiện SH7014
Giải thích chi tiết về linh kiện  32-Bit RISC Microcomputer
PDF  754 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7014 bảng dữ liệu(HTML) 174 Page - Renesas Technology Corp

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8. Bus State Controller (BSC)
Rev.5.00 Sep. 27, 2007 Page 140 of 716
REJ09B0398-0500
8.6
Waits between Access Cycles
When a read from a slow device is completed, data buffers may not go off in time to prevent data
conflicts with the next access. If there is a data conflict during memory access, the problem can be
solved by inserting a wait in the access cycle.
To enable detection of bus cycle starts, waits can be inserted between access cycles during
continuous accesses of the same CS space by negating the
CSn signal once.
8.6.1
Prevention of Data Bus Conflicts
For the two cases of write cycles after read cycles, and read cycles for a different area after read
cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of
the BCR2 and the DIW of the DCR occur. When idle cycles already exist between access cycles,
only the number of empty cycles remaining beyond the specified number of idle cycles are
inserted.
Figure 8.20 shows an example of idles between cycles. In this example, 1 idle between CSn space
cycles has been specified, so when a CSm space write immediately follows a CSn space read
cycle, 1 idle cycle is inserted.



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