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SH7014 bảng dữ liệu(PDF) 160 Page - Renesas Technology Corp

tên linh kiện SH7014
Giải thích chi tiết về linh kiện  32-Bit RISC Microcomputer
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SH7014 bảng dữ liệu(HTML) 160 Page - Renesas Technology Corp

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8. Bus State Controller (BSC)
Rev.5.00 Sep. 27, 2007 Page 126 of 716
REJ09B0398-0500
8.3.3
CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the
RD signal or WRx signal assert period
beyond the length of the
CSn signal assert period by setting the SW3 to SW0 bits of BCR2. This
allows for flexible interfaces with external circuitry. The timing is shown in figure 8.6. T
h and Tf
cycles are added respectively before and after the ordinary cycle. Only
CSn is asserted in these
cycles;
RD and WRx signals are not. Further, data is extended up to the T
f cycle, which is
effective for gate arrays and the like, which have slower write operations.
Th
T1
CK
Read
Write
Address
CSn
RD
Data
WRx
Data
DACK
T2
Tf
Figure 8.6
CS Assert Period Extension Function



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