H8S2245 datasheet(212/818 Pages) RENESAS

tên linh kiện	H8S2245

Giải thích chi tiết về linh kiện	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

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Section 6 Bus Controller

Rev.3.00 Mar. 26, 2007 Page 170 of 772

REJ09B0355-0300

(2) Write after Read

If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle

cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal

mode.

Figure 6.21 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an

idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and

the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.

Address bus

Bus cycle A

Data bus

Bus cycle B

Long output

floating time

Data

collision

Address bus

Bus cycle A

Data bus

Bus cycle B

HWR

CS (area A)

CS (area B)

CS (area A)

CS (area B)

(a) Idle cycle not inserted

(ICIS0 = 0)

(b) Idle cycle inserted

(Initial value ICIS0 = 1)

Figure 6.21 Example of Idle Cycle Operation (2)

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