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H8S2245 bảng dữ liệu(PDF) 17 Page - Renesas Technology Corp |
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H8S2245 bảng dữ liệu(HTML) 17 Page - Renesas Technology Corp |
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17 / 818 page ![]() Rev.3.00 Mar. 26, 2007 Page xvii of xlii REJ09B0355-0300 Item Page Revision (See Manual for Details) 12.2.7 Serial Status Register (SSR) 417 Bit 7 Transmit Data Register Empty (TDRE) Note * added [Clearing conditions] • When 0 is written to ... • When the DTC* is activated by a TXI interrupt and write data to TDR Note: * DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 418 Bit 6 Receive Data Register Full (RDRF) Note * added [Clearing conditions] • When 0 is written to ... • When the DTC* is activated by a RXI interrupt and write data to RDR Notes: RDR and the RDRF flag are not affected ... * DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. 420 Bit 2 Transmit End (TEND) Note * added [Clearing conditions] • When 0 is written to ... • When the DTC* is activated by a TXI interrupt and write data to TDR Note: * DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0. |
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