H8S2245 datasheet(420/818 Pages) RENESAS

420 / 818 page

Section 10 8-Bit Timers

Rev.3.00 Mar. 26, 2007 Page 378 of 772

REJ09B0355-0300

10.3.5

Operation with Cascaded Connection

If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two

channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer

mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1

(compare match counter mode). In this case, the timer operates as below.

16-Bit Counter Mode

When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer

with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.

• Setting of compare match flags

 The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs.

 The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs.

• Counter clear specification

 If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match,

the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare match

event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter

clear by the TMRI0 pin has also been set.

 The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot

be cleared independently.

• Pin output

 Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with

the 16-bit compare match conditions.

 Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with

the lower 8-bit compare match conditions.

Compare Match Counter Mode

When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare match A's for channel 0.

Channels 1 and 0 are controlled independently. Conditions such as setting of the CMF flag,

generation of interrupts, output from the TMO pin, and counter clear are in accordance with the

settings for each channel.

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