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H8S2245 bảng dữ liệu(PDF) 416 Page - Renesas Technology Corp |
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H8S2245 bảng dữ liệu(HTML) 416 Page - Renesas Technology Corp |
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416 / 818 page ![]() Section 10 8-Bit Timers Rev.3.00 Mar. 26, 2007 Page 374 of 772 REJ09B0355-0300 10.3 Operation 10.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock Three different internal clock signals ( φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 10.2 shows the count timing. φ Internal clock Clock input to TCNT TCNT N–1 N N+1 Figure 10.2 Count Timing for Internal Clock Input External Clock Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising edge, the falling edge, and both rising and falling edges. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Figure 10.3 shows the timing of incrementation at both edges of an external clock signal. |
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