M16CSLASH29 datasheet(285/499 Pages) RENESAS

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16. MULTI-MASTER I2C bus INTERFACE

page 261

Figure 16.6 S3D0 Register

0: SCL output logic value = 0

1: SCL output logic value = 1

0: SDA output logic value = 0

1: SDA output logic value = 1

0: SCL I/O pin

1: Port output pin

0: SDA I/O pin

1: Port output pin

0: Disable the I2C bus interface

interrupt of data receive

completion

1: Enable the I2C bus interface

interrupt of data receive

completion

When setting NACK

(ACK bit = 0), write 0

0: Disable the I2C bus interface

interrupt of STOP condition

detection

1: Enable the I2C bus interface

interrupt of STOP condition

detection

I C bus system clock

selection bits,

if bits ICK4 to ICK2 in the

S4D0 register is 0002

The logic value monitor

bit of SCL output

The logic value monitor

bit of SDA output

SCL/port function switch

bit(1)

SDA/port function switch

bit(1)

The interrupt enable bit for

data receive completion

The interrupt enable bit for

STOP condition detection

ICK1

ICK0

SCLM

SDAM

PEC

PED

WIT

SIM

Function

Bit Name

Bit Symbol

001100002

After Reset

02E616

Address

Symbol

S3D0

C0 Control Register 1

b7 b6 b5 b4 b3 b2b1b0

b7 b6

0 0 :

0 1 :

1 0 :

VIIC =1/2 fIIC

=1/4fIIC

=1/8 fIIC

1 1 : Reserved

VIIC

NOTE:

1. Bits PED and PEC are enabled when the ES0 bit in the S1D0 register is set to 1 (I2C bus interface enabled).

2. When the PCLK0 bit in the PCLKR register is set to 0, fIIC=f2. When the PCLK0 bit in the PCLKR register is set

to 1, fIIC=f1.

(2)

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