M16CSLASH29 datasheet(230/499 Pages) RENESAS

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14. Serial I/O

page 206

14.1.4 Special Mode 2 (UART2)

Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are

selectable. Table 14.15 lists the specifications of Special Mode 2. Table 14.16 lists the registers used in

Special Mode 2 and the register values set. Figure 14.26 shows communication control example for

Special Mode 2.

Table 14.15 Special Mode 2 Specifications

Item

Specification

Transfer data format

• Transfer data length: 8 bits

Transfer clock

• Master mode

the CKDIR bit in the U2MR register is set to 0 (internal clock) : fj/ (2(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in the U2BRG register

0016 to FF16

• Slave mode

CKDIR bit is set to 1 (external clock selected) : Input from CLK2 pin

Transmit/receive control

Controlled by input/output ports

Transmission start condition • Before transmission can start, the following requirements must be met (1)

_ The TE bit in the U2C1 register is set to 1 (transmission enabled)

_ The TI bit in the U2C1 register is set to 0 (data present in U2TB register)

Reception start condition

• Before reception can start, the following requirements must be met (1)

_ The RE bit in the U2C1 register is set to 1 (reception enabled)

_ The TE bit in the U2C1 register is set to 1 (transmission enabled)

_ The TI bit in the U2C1 register is set to 0 (data present in the U2TB register)

• For transmission, one of the following conditions can be selected

_ The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty): when trans

ferring data from the U2TB register to the UART2 transmit register (at start of transmission)

_ The U2IRS bit is set to 1 (transfer completed): when the serial I/O finished sending

data from the UART2 transmit register

• For reception

When transferring data from the UART2 receive register to the U2RB register (at

completion of reception)

Error detection

• Overrun error (2)

This error occurs if the serial I/O started receiving the next data before reading the

U2RB register and received the 7th bit in the the next data

Select function

• Clock phase setting

Selectable from four combinations of transfer clock polarities and phases

Interrupt request

generation timing

NOTES:

1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the U2C0 register is set to

0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the

external clock is in the high state; if the CKPOL bit in the U2C0 register is set to 1 (transmit data output at the rising

edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.

2. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC register remains

unchanged.

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