M16CSLASH29 datasheet(209/499 Pages) RENESAS

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14. Serial I/O

page 185

14.1.1.2 CLK Polarity Select Function

Use the CKPOL bit in the UiC0 register (i=0 to 2) to select the transfer clock polarity. Figure 14.11

shows the polarity of the transfer clock.

Figure 14.11 Polarity of transfer clock

14.1.1.3 LSB First/MSB First Select Function

Use the UFORM bit in the UiC0 register (i=0 to 2) to select the transfer format. Figure 14.12 shows

the transfer format.

Figure 14.12 Transfer format

(2) When the CKPOL bit in the UiC0 register is set to 1 (transmit data output at the rising

edge and the receive data taken in at the falling edge of the transfer clock)

TXDi

RXDi

CLKi

(1) When the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge

and the receive data taken in at the rising edge of the transfer clock)

TXDi

RXDi

CLKi

(2)

(3)

i = 0 to 2

NOTES:

1. This applies to the case where the UFORM bit in the UiC0 register is set to 0 (LSB first) and the

UiLCH bit in the UiC1 register is set to 0 (no reverse).

2. When not transferring, the CLKi pin outputs a high signal.

(1) When the UFORM bit in the UiC0 register 0 (LSB first)

TXDi

RXDi

CLKi

(2) When the UFORM bit in the UiC0 register is set to 1 (MSB first)

TXDi

RXDi

CLKi

i = 0 to 2

NOTE:

1. This applies to the case where the CKPOL bit in the UiC0 register is set to 0 (transmit data output at

the falling edge and the receive data taken in at the rising edge of the transfer clock) and the

UiLCH bit in the UiC1 register 0 (no reverse).

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