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10. Interrupts

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10.6 Interrupt Request Reception

Software interrupts and special interrupts occur when conditions to generate an interrupt are met.

The peripheral function interrupts are acknowledged when all conditions below are met.

• I flag

= "1"

• IR bit

= "1"

• ILVL2 to ILVL0 bits

> IPL

The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the

FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register.

10.6.1 I Flag and IPL

The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable

interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically

set to "0" after reset.

IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7.

If a requested interrupt has higher priority than that indicated by IPL, the interrupt is acknowledged.

Table 10.3 lists interrupt priority levels associated with IPL.

Table 10.3 Interrupt Priority Levels

IPL2

IPL1

IPL0

Interrupt Priority Levels

Level 1 and above

Level 2 and above

Level 3 and above

Level 4 and above

Level 5 and above

Level 6 and above

Level 7 and above

All maskable interrupts are disabled

10.6.2 Interrupt Control Register and RLVL Register

The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 10.3

and 10.4 show the interrupt control register. Figure 10.5 shows the RLVL register.

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