ORSPI4 datasheet(184/263 Pages) LATTICE

tên linh kiện	ORSPI4

Giải thích chi tiết về linh kiện	Dual SPI4 Interface and High-Speed SERDES FPSC

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

184

Figure 96. Status Channel Reference Points with Respect to Clock Edge (Edge Aligned Legacy Mode)

Table 64. Status Path Interface ORSPI4 Timing in Legacy Mode

Note: This table compares the OIF Speciﬁcation requirements vs. the ORSPI4 Speciﬁcation. There is no OIF Speciﬁcation for LVDS buffers.

ORSPI4 Timing in

Legacy Mode

Symbol

Description

Min

Max

Units

TDCLK/RDCLK frequency

450

MHz

TSCLK/RSCLK frequency

112.5

MHz

—

TSCLK/RSCLK duty cycle

tdia

Data invalid window with respect to clock edge

(Reference point C)

—

0.3

tdib

Data invalid window with respect to clock edge

(Reference point C)

—

0.45

tS*

Setup time for TSTAT with respect to TSCLK -

LVTTL Buffers (Reference point D)

0.5

—

Setup time for TSTAT with respect to TSCLK -

LVDS Buffers (Reference point D)

0.7

—

tH*

Hold time for TSTAT with respect to TSCLK -

LVTTL Buffers (Reference point D)

1.2

—

Hold time for TSTAT with respect to TSCLK -

LVDS Buffers (Reference point D)

1.0

—

RSCLK

RSTAT

(C)

Launch Edge

dia

dib

(D)

Capture Edge

TSCLK

TSTAT

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