ORSPI4 datasheet(154/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

154

The following table describes the different methods of resetting various parts of the EAC. It lists the logic values set

on the FPGA interface and the primary ASB pins.

Table 44. ORSPI4 RESET

1. Please refer to the ORCA SERIES 4 FPGA data sheet at www.latticesemi.com.

I/O TRI-STATE Functions

The EAC I/Os can be tri-stated using one of the three signals below.

TS_ALL

This is an FPGA signal that globally tri-states all EAC IOs in addition to the FPGA IOs. For more information on

TS_ALL, please refer to the ORCA SERIES 4 FPGA data sheet at http://www.latticesemi.com.

TRISTN

This is an ORSPI4 EAC active low IO that globally tri-states all EAC IOs.

Power-Up

In addition to its RESET function, power-up also puts the ORSPI4 FPSC IO in tri-state until the chip is fully pow-

ered up.

Power Down

When set low, the ORSPI4 FPSC “PDN” powers down the following:

• all PLLs in the SPIA, SPIB, Memory Controller and SERDES

• LVDS and HSTL buffers on the EAC section of the ORSPI4

• SPIA, SPIB, and SERDES logic

Signal Name

RESET Type

ORSPI4 Core Affected

MPI

SPIA

SPIB

M_CTRL

SERDES

PWRUPRES = 1

FPGA signal

•

DONE = 0

FPGA I/O

•

RESETN = 0

EAC IO

•

GSRN = 0 and

GSRN_DISABLE = 0

FPGA signal

•

FPGA_RESET_S4A = 1

Interface Signal

•

SOFT_RESET_S4A = 1

Software Register Bit

•

FPGA_RESET_S4B = 1

Interface Signal

•

SOFT_RESET_S4B = 1

Software Register Bit

•

FPGA_RESET_MC = 1

Interface Signal

•

SOFT_RESET_MC = 1

Software Register Bit

•

FPGA_RESET_FC = 1

Interface Signal

•

HARD_RESET_FC = 1

Software Register Bit

•

SYS_RST_N (Channel

Alignment FIFO RESET)

Interface Signal

•

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