ORSPI4 datasheet(141/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

141

Figure 76. Read Data and Instruction Word Formats

Figure 77. ORSPI4 Memory Controller Interface to FPGA — Read Timing Diagram

The user can write/read instructions into the read instruction FIFO as long as the MC_RIFIFO_FULL ﬂag is low. If

this ﬂag is high, the FIFO can accept one more instruction. The user can start reading data from the read data

FIFO once the MC_RFIFO_EMPTY ﬂag goes low.

It is the responsibility of the user to:

• Maintain count of data from the read data FIFO and check if they match the data length provided in the corre-

sponding instruction word

• Associate the data received with the address. Data will be received in the same order as they were requested.

The timing diagram for the read interface for a typical read sequence is shown in Figure 77. The read sequence in

this case consists of reading 2 words from location A0 followed by one word each from locations A1, A2, eight

words from A3 and one word from A4 and A5. The MC_RIFIFO_FULL is asserted after the instruction for location

A2 has been written, indicating that only one more instruction may be written to the instruction FIFO. The read

instruction write to access location A4 cannot occur until the MC_RIFIFO_FULL ﬂag is deasserted. The

MC_RDFIFO_EMPTY ﬂag remains high until data has been read from the QDRII SRAM and is available to the

FPGA logic.

Read Data

Read Data Word

Address

Data Length

Read Instruction Word

Reserved (low)

F_MC_RCLK

F_MC_RIFIFO_WE

F_MC_RI(23:18)

F_MC_RI(17:0)

MC_RIFIFO_FULL

MC_RDFIFO_EMPTY

F_MC_RDFIFO_RE

MC_RD(71:0)

D4*1

D0*2

D1*1

D2*1

D3*8

D0-1

D1-0

D2-0

D0-0

D1-0

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