C167CS datasheet(125/517 Pages) INFINEON

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C167CS

Derivatives

Clock Generation

User’s Manual

6-7

V2.0, 2000-07

The PLL constantly synchronizes to the external clock signal. Due to the fact that the

external frequency is 1/F’th of the PLL output frequency the output frequency may be

slightly higher or lower than the desired frequency. This jitter is irrelevant for longer time

periods. For short periods (1 … 4 CPU clock cycles) it remains below 4%.

Figure 6-6

PLL Block Diagram

Table 6-1

C167CS Clock Generation Modes

RP0H.7-5

(P0H.7-5)

CPU Frequency

fCPU = fOSC × F

External Clock

Input Range1)

1) The external clock input range refers to a CPU clock range of 10 … 33 MHz.

Notes

1 1 1

fOSC × 4

2.5 to 8.25 MHz

Default configuration

1 1 0

fOSC × 3

3.33 to 11 MHz

–

10 1

fOSC × 2

5 to 16.5 MHz

–

1 0 0

fOSC × 5

2 to 6.6 MHz

–

0 1 1

fOSC × 1

1 to 33 MHz

Direct drive 2)

2) The maximum frequency depends on the duty cycle of the external clock signal. In emulation mode pin P0.15

(P0H.7) is inverted, i.e. the configuration ‘111’ would select direct drive in emulation mode.

0 1 0

fOSC × 1.5

6.66 to 22 MHz

–

0 0 1

fOSC / 2

2 to 66 MHz

CPU clock via prescaler

0 0 0

fOSC × 2.5

4 to 13.2 MHz

–

MCB04339

PLL Circuit

PLL = F × fIN

Reset

PWRDN

PLL

CPU

OWD

Reset

Sleep

Lock

XP3INT

CLKCFG

(RP0H.7-5)

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