C167CS datasheet(95/517 Pages) INFINEON

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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-12

V2.0, 2000-07

5.2

Operation of the PEC Channels

The C167CS’s Peripheral Event Controller (PEC) provides 8 PEC service channels,

which move a single byte or word between two locations in segment 0 (data pages

3 … 0). This is the fastest possible interrupt response and in many cases is sufficient to

service the respective peripheral request (e.g. serial channels, etc.). Each channel is

controlled by a dedicated PEC Channel Counter/Control register (PECCx) and a pair of

pointers for source (SRCPx) and destination (DSTPx) of the data transfer.

The PECC registers control the action that is performed by the respective PEC channel.

PECCx

PEC Control Reg.

SFR (FECyH/6zH, see Table 5-4)

Reset Value: 0000H

98765

43210

INC

BWT

COUNT

Bit

Function

COUNT

PEC Transfer Count

Counts PEC transfers and influences the channel’s action (see Table 5-5)

BWT

Byte/Word Transfer Selection

Transfer a Word

Transfer a Byte

INC

Increment Control (Modification of SRCPx or DSTPx)

0 0:

Pointers are not modified

0 1:

Increment DSTPx by 1 or 2 (BWT)

1 0:

Increment SRCPx by 1 or 2 (BWT)

1 1:

Reserved. Do not use this combination.

(changed to ‘10’ by hardware)

Table 5-4

PEC Control Register Addresses

Address

Reg. Space

Address

Reg. Space

PECC0

FEC0H/60H

SFR

PECC4

FEC8H/64H

SFR

PECC1

FEC2H/61H

SFR

PECC5

FECAH/65H

SFR

PECC2

FEC4H/62H

SFR

PECC6

FECCH/66H

SFR

PECC3

FEC6H/63H

SFR

PECC7

FECEH/67H

SFR

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