C167CS datasheet(20/517 Pages) INFINEON

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C167CS

Derivatives

Architectural Overview

User’s Manual

2-3

V2.0, 2000-07

2.1.1

High Instruction Bandwidth/Fast Execution

Based on the hardware provisions, most of the C167CS’s instructions can be executed

in just one machine cycle, which requires 2 CPU clock cycles (2

× 1 / f

CPU = 4 TCL). For

example, shift and rotate instructions are always processed within one machine cycle,

independent of the number of bits to be shifted.

Branch-, multiply- and divide instructions normally take more than one machine cycle.

These instructions, however, have also been optimized. For example, branch

instructions only require an additional machine cycle, when a branch is taken, and most

branches taken in loops require no additional machine cycles at all, due to the so-called

‘Jump Cache’.

A 32-bit/16-bit division takes 20 CPU clock cycles, a 16-bit

× 16-bit multiplication takes

10 CPU clock cycles.

The instruction cycle time has been dramatically reduced through the use of instruction

pipelining. This technique allows the core CPU to process portions of multiple sequential

instruction stages in parallel. The following four stage pipeline provides the optimum

balancing for the CPU core:

FETCH: In this stage, an instruction is fetched from the internal ROM or RAM or from

the external memory, based on the current IP value.

DECODE: In this stage, the previously fetched instruction is decoded and the required

operands are fetched.

EXECUTE: In this stage, the specified operation is performed on the previously fetched

operands.

WRITE BACK: In this stage, the result is written to the specified location.

If this technique were not used, each instruction would require four machine cycles. This

increased performance allows a greater number of tasks and interrupts to be processed.

Instruction Decoder

Instruction decoding is primarily generated from PLA outputs based on the selected

opcode. No microcode is used and each pipeline stage receives control signals staged

in control registers from the decode stage PLAs. Pipeline holds are primarily caused by

wait states for external memory accesses and cause the holding of signals in the control

registers. Multiple-cycle instructions are performed through instruction injection and

simple internal state machines which modify required control signals.

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