NRF52810-QFAA-R datasheet(252/483 Pages) NORDIC

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Peripherals

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RW Field

Value Id

Value

Description

RW TEP

Pointer to task register

6.12 PWM — Pulse width modulation

The PWM module enables the generation of pulse width modulated signals on GPIO. The module

implements an up or up-and-down counter with four PWM channels that drive assigned GPIOs.

Three PWM modules can provide up to 12 PWM channels with individual frequency control in groups

of up to four channels. Furthermore, a built-in decoder and EasyDMA capabilities make it possible to

manipulate the PWM duty cycles without CPU intervention. Arbitrary duty-cycle sequences are read from

Data RAM and can be chained to implement ping-pong buffering or repeated into complex loops.

Listed here are the main features of one PWM module:

• Fixed PWM base frequency with programmable clock divider

• Up to four PWM channels with individual polarity and duty-cycle values

• Edge or center-aligned pulses across PWM channels

• Multiple duty-cycle arrays (sequences) defined in Data RAM

• Autonomous and glitch-free update of duty cycle values directly from memory through EasyDMA

• Change of polarity, duty-cycle, and base frequency possibly on every PWM period

• Data RAM sequences can be repeated or connected into loops

Decoder

Sequence 0

Sequence 1

Wave Counter

DATA RAM

COMP0

COMP1

COMP2

COMP3

SEQSTARTED[0]

SEQSTARTED[1]

SEQEND[0]

SEQEND[1]

SEQ[n].REFRESH

NEXTSTEP

PSEL.OUT[0]

PSEL.OUT[1]

PSEL.OUT[2]

PSEL.OUT[3]

PWM

Carry/Reload

PRESCALER

PWM_CLK

START

STOP

SEQSTART[0]

SEQSTART[1]

COUNTERTOP

STARTED

STOPPED

Figure 47: PWM module

6.12.1 Wave counter

The wave counter is responsible for generating the pulses at a duty-cycle that depends on the compare

values, and at a frequency that depends on COUNTERTOP.

There is one common 15-bit counter with four compare channels. Thus, all four channels will share the

same period (PWM frequency), but can have individual duty-cycle and polarity. The polarity is set by the

value read from RAM (see Decoder memory access modes on page 257), while the MODE register

controls if the counter counts up, or up and down. The timer top value is controlled by the COUNTERTOP

4430_161 v1.0

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