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NRF52810-QFAA-R bảng dữ liệu(PDF) 191 Page - Nordic Semiconductor |
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NRF52810-QFAA-R bảng dữ liệu(HTML) 191 Page - Nordic Semiconductor |
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191 / 483 page  Peripherals Register Offset Description TASKS_CLR[0] 0x060 Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low. TASKS_CLR[1] 0x064 Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it low. TASKS_CLR[2] 0x068 Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is to set it low. TASKS_CLR[3] 0x06C Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is to set it low. TASKS_CLR[4] 0x070 Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is to set it low. TASKS_CLR[5] 0x074 Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is to set it low. TASKS_CLR[6] 0x078 Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is to set it low. TASKS_CLR[7] 0x07C Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is to set it low. EVENTS_IN[0] 0x100 Event generated from pin specified in CONFIG[0].PSEL EVENTS_IN[1] 0x104 Event generated from pin specified in CONFIG[1].PSEL EVENTS_IN[2] 0x108 Event generated from pin specified in CONFIG[2].PSEL EVENTS_IN[3] 0x10C Event generated from pin specified in CONFIG[3].PSEL EVENTS_IN[4] 0x110 Event generated from pin specified in CONFIG[4].PSEL EVENTS_IN[5] 0x114 Event generated from pin specified in CONFIG[5].PSEL EVENTS_IN[6] 0x118 Event generated from pin specified in CONFIG[6].PSEL EVENTS_IN[7] 0x11C Event generated from pin specified in CONFIG[7].PSEL EVENTS_PORT 0x17C Event generated from multiple input GPIO pins with SENSE mechanism enabled INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt CONFIG[0] 0x510 Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event CONFIG[1] 0x514 Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event CONFIG[2] 0x518 Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event CONFIG[3] 0x51C Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event CONFIG[4] 0x520 Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event CONFIG[5] 0x524 Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event CONFIG[6] 0x528 Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event CONFIG[7] 0x52C Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event Table 41: Register Overview 6.9.4.1 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description A RW IN0 Write '1' to Enable interrupt for IN[0] event See EVENTS_IN[0] Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled B RW IN1 Write '1' to Enable interrupt for IN[1] event See EVENTS_IN[1] Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled C RW IN2 Write '1' to Enable interrupt for IN[2] event See EVENTS_IN[2] Set 1 Enable 4430_161 v1.0 191 |
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