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NRF52810-QFAA-R bảng dữ liệu(PDF) 455 Page - Nordic Semiconductor

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Giải thích chi tiết về linh kiện  RF52810
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NRF52810-QFAA-R bảng dữ liệu(HTML) 455 Page - Nordic Semiconductor

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Peripherals
The watchdog must be configured before it is started. After it is started, the watchdog’s configuration
registers, which comprise registers CRV, RREN, and CONFIG, will be blocked for further configuration.
The watchdog can be reset from several reset sources, see Reset behavior on page 66.
When the device starts running again, after a reset, or waking up from OFF mode, the watchdog
configuration registers will be available for configuration again.
6.26.4 Registers
Base address
Peripheral
Instance
Description
Configuration
0x40010000
WDT
WDT
Watchdog timer
Table 96: Instances
Register
Offset
Description
TASKS_START
0x000
Start the watchdog
EVENTS_TIMEOUT
0x100
Watchdog timeout
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
RUNSTATUS
0x400
Run status
REQSTATUS
0x404
Request status
CRV
0x504
Counter reload value
RREN
0x508
Enable register for reload request registers
CONFIG
0x50C
Configuration register
RR[0]
0x600
Reload request 0
RR[1]
0x604
Reload request 1
RR[2]
0x608
Reload request 2
RR[3]
0x60C
Reload request 3
RR[4]
0x610
Reload request 4
RR[5]
0x614
Reload request 5
RR[6]
0x618
Reload request 6
RR[7]
0x61C
Reload request 7
Table 97: Register Overview
6.26.4.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
Value Id
Value
Description
A
RW TIMEOUT
Write '1' to Enable interrupt for TIMEOUT event
See EVENTS_TIMEOUT
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
6.26.4.2 INTENCLR
Address offset: 0x308
4430_161 v1.0
455



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