ADIS16505-2SLASHPCBZ datasheet(17/41 Pages) AD

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Data Sheet

ADIS16505

Rev. C | Page 17 of 41

SPI

The SPI provides access to the user registers (see Table 9).

Figure 34 shows the most common connections between the

ADIS16505 and a SPI master device, which is often an

embedded processor that has a SPI-compatible interface. In this

example, the SPI master uses an interrupt service routine to

collect data every time the data ready (DR) signal pulses.

Figure 34 shows the typical SPI connection. The 33 Ω series

resistors shown in Figure 34 are recommended but not required.

Additional information on the SPI can be found in the

Applications Information section.

SYSTEM

PROCESSOR

SPI MASTER

VDD

I/O LINES ARE COMPATIBLE WITH

3.3V CMOS LOGIC LEVELS

TERMINATION RESISTORS

ARE RECOMMENDED

BUT OPTIONAL

SCLK

DIN

DOUT

SCLK

MOSI

IRQ

MISO

ADIS16505

+3.3V

33Ω

Figure 34. Electrical Connection Diagram

Table 6 provides an example list of pin names for the SPI port

in an embedded processor.

Table 6. Generic SPI Master Pin Names and Functions

Mnemonic

Function

Slave select

SCLK

Serial clock

MOSI

Master output, slave input

MISO

Master input, slave output

IRQ

Interrupt request

Embedded processors typically configure their serial ports for

communicating with SPI slave devices such as the ADIS16505 by

using control registers on the processor itself. Table 7 lists the

SPI protocol settings for the ADIS16505.

Table 7. Generic Master Processor SPI Settings

Processor Setting

Description

Master

ADIS16505 operates as slave

SCLK ≤ 2 MHz1

Maximum serial clock rate

SPI Mode 3

CPOL = 1 (polarity), CPHA = 1 (phase)

MSB First Mode

Bit sequence, see Figure 40 for coding

16-Bit Mode

Shift register and data length

1 A burst mode read requires this value to be ≤1 MHz (see Table 2 for more

information).

DATA READY (DR)

The factory default configuration provides users with a DR

signal on the DR pin (see Table 5), which pulses when the output

data registers are updating. Connect the DR pin to an input pin

on the embedded processor and configure this pin to trigger data

collection on the second edge of the pulse on the DR pin. The

MSC_CTRL register, Bit 0 (see Table 106), controls the polarity

of this signal. In Figure 35 shows a DR signal with

must start on the rising edges of the DR pulses.

ACTIVE

INACTIVE

Figure 35. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default)

During the start-up and reset recovery processes, the DR signal

can exhibit some transient behavior before data production

begins. Figure 36 shows an example of the DR behavior during

startup, and Figure 37 and Figure 38 provide examples of the

DR behavior during recovery from reset commands.

VDD

START-UP TIME

TIME THAT VDD > 3V

PULSING INDICATES

DATA PRODUCTION

Figure 36. Data Ready Response During Startup

RESET RECOVERY TIME

SOFTWARE RESET COMMAND

GLOB_CMD, BIT 7 = 1

DR PULSING

RESUMES

Figure 37. Data Ready Response During Reset Recovery

(Register GLOB_CMD, Bit 7 = 1)

RST

RESET RECOVERY TIME

RST PIN

RELEASED

DR PULSING

RESUMES

Figure 38. Data Ready Response During Reset (RST = 0) Recovery

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