Data Sheet

ADIS16505

Rev. C | Page 5 of 41

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS5

Input Voltage

High, VIH

2.0

V

Low, VIL

0.8

V

RST Pulse Width

1

μs

Input Current

Logic 1, IIH

VIH = 3.3 V

10

μA

Logic 0, IIL

VIL = 0 V

All Pins Except RST

10

μA

RST Pin

0.33

mA

Input Capacitance, CIN

10

pF

DIGITAL OUTPUTS

Output Voltage

High, VOH

Source current (ISOURCE) = 0.5 mA

2.4

V

Low, VOL

Sink current (ISINK) = 2.0 mA

0.4

V

FLASH MEMORY

Endurance6

10,000

Cycles

Data Retention7

TJ = 85°C

20

Years

FUNCTIONAL TIMES8

Time until data is available

Power-On Start-Up Time

310

ms

Reset Recovery Time9

GLOB_CMD, Bit 7 = 1 (see Table 112)

255

ms

Factory Calibration Restore

GLOB_CMD, Bit 1 = 1 (see Table 112)

136

ms

Flash Memory Backup

GLOB_CMD, Bit 3 = 1 (see Table 112)

70

ms

Flash Memory Test Time

GLOB_CMD, Bit 4 = 1 (see Table 112)

30

ms

Self Test Time10

GLOB_CMD, Bit 2 = 1 (see Table 112)

24

ms

CONVERSION RATE

2000

SPS

Initial Clock Accuracy

3

%

Sync Input Clock

1.9

2.1

kHz

POWER SUPPLY, VDD

Operating voltage range

3.0

3.6

V

Power Supply Current11

Normal mode, VDD = 3.3 V

44

55

mA

1 Cross-axis sensitivity is the sine of this number.

2 This measurement is based on the deviation from a best fit linear model.

3 Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of high temperature operating life (HTOL) at 105°C.

4 All specifications associated with the accelerometers relate to the full-scale range of ±8 g, unless otherwise noted.

5 The digital input/output signals use a 3.3 V system.

6 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.

7 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.

8 These times do not include thermal settling and internal filter response times, which may affect overall accuracy.

9 The RST line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery.

10 The self test time can extend when using external clock rates lower than 2000 Hz.

11 Power supply current transients can reach 100 mA during initial startup or reset recovery.