ADIS16505-2SLASHPCBZ datasheet(15/41 Pages) AD

15 / 41 page

Data Sheet

ADIS16505

Rev. C | Page 15 of 41

THEORY OF OPERATION

INTRODUCTION

Figure 30 provides the basic signal chain for the accelerometers

and gyroscopes of the ADIS16505. When using the factory

default configuration, the ADIS16505 initializes itself at power-

up and automatically starts a continuous process of sampling,

processing, and loading calibrated sensor data into its output

registers at a rate of 2000 SPS.

CLOCK CONTROL

The ADIS16505 provides four modes of operation with respect

to the source of the sampling and processing clock (see the

frequency sampling clock (fSM) in Figure 30): internal, direct

input sync, scaled sync, and output sync. The MSC_CTRL

selection of these modes.

Note that changes to the MSC_CTRL[3:2] and UP_SCALE

registers are only updated for readback after the internal clock

configuration is complete. Therefore, the user must wait until

the DR pin toggles before attempting to verify the desired

settings by reading the values of these registers. Changes to

MSC_CTRL[9:6] may take up to 200 μs after writing to indicate

to the new value during readback. The external clock must also

be present for two external clock cycles if either direct input

sync mode or scaled sync mode is programmed.

Internal Clock Mode

Setting MSC_CTRL register, Bits[3:2] = 00 selects the internal

clock mode and is the default. In this mode, the ADIS16505

uses an internally generated clock that has a nominal frequency

of 2000 Hz to drive sampling and data processing for each

sensor and associated signal chain.

Direct Input Sync Mode

Setting MSC_CTRL register, Bits[3:2] = 01 selects direct input

sync mode and allows fSM to come directly from an external

clock to control the sensor sampling using the SYNC pin as an

input. When operating in input sync mode, the ADIS16505

performs best when the external clock frequency (fSYNC) is

between 1900 Hz and 2100 Hz.

Scaled Sync Mode

Setting MSC_CTRL register, Bits[3:2] = 10 selects scaled sync

mode, which supports use of an external sync clock between

1 Hz and 128 Hz that can come from video systems or global

positioning systems (GPSs). When operating in scaled sync

mode, the frequency of the sample clock is equal to the product

of the external clock scale factor, KECSF (from the UP_SCALE

the clock signal on the SYNC pin. As in input sync mode, the

ADIS16505 performs best when fSM is between 1900 Hz and

2100 Hz.

Changes to the UP_SCALE register value resets the clock

multiplication phase-locked loop (PLL) and restarts the locking

process. The locking process starts with an input reference

clock edge resetting the feedback clock edge, and lock is declared

when time differences between these two edges is ≤100 μs.

For example, when using a 1 Hz input signal, set UP_SCALE =

0x07D0 (KECSF = 2000 (decimal)) to establish a sample rate of

2000 SPS for the inertial sensors and their signal processing.

Use the following sequence on the DIN pin to configure

UP_SCALE for this scenario: 0xE2D0, then 0xE307.

Output Sync Mode

When Register MSC_CTRL, Bits[3:2] = 11, the ADIS16505

operates in output sync mode, which is the same as internal

clock mode except that the SYNC pin pulses when the internal

processor collects data from the inertial sensors. Figure 29

provides an example of this signal.

SYNC

500µs

GYROSCOPE AND

ACCELEROMETER

DATA ACQUISITION

Figure 29. Sync Output Signal, Register MSC_CTRL, Bits[3:2] = 11

BARTLETT

WINDOW

FILTER

CALIBRATION

DECIMATION

FILTER

OUTPUT

DATA

REGISTERS

CONTROL

REGISTERS

CLOCK

CONTROL

SERIAL

PERIPHERAL

INTERFACE

SYNC PIN

(

fSYNC)

fSM

fODR

DIGITAL

FILTER

ACCELEROMETER/

GYROSCOPE

Figure 30. Sensor Signal Chain

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