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ADIS16505-2/PCBZ bảng dữ liệu(PDF) 33 Page - Analog Devices

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Data Sheet
ADIS16505
Rev. C | Page 33 of 41
Filter Control Register (FILT_CTRL)
Table 101. FILT_CTRL Register Definition
Addresses
Default
Access
Flash Backup
0x5C, 0x5D
0x0000
R/W
Yes
Table 102. FILT_CTRL Bit Definitions
Bits
Description
[15:3]
Not used
[2:0]
Filter Size Variable B; number of taps in each stage; N = 2B,
where B = 0 to 6 (decimal). Changes to this register may
take up to 30 μs after writing to indicate the new value
during readback.
The FILT_CTRL register (see Table 101 and Table 102) provides
user controls for the Bartlett window FIR filter (see Figure 31),
which contains two cascaded averaging filters. For example, use
the following sequence to set Register FILT_CTRL, Bits[2:0] =
0100, which sets each stage to have 16 taps: 0xCC04 and 0xCD00.
Figure 58 provides the frequency response for several settings in
the FILT_CTRL register.
0
–20
–40
–60
–80
–100
–120
–140
0.001
0.01
0.1
1
FREQUENCY (
f/fS)
N = 2
N = 4
N = 16
N = 64
Figure 58. Bartlett Window, FIR Filter Frequency Response
(Phase Delay = N Samples)
Range Identifier (RANG_MDL)
Table 103. RANG_MDL Register Definition
Addresses
Default
Access
Flash Backup
0x5E, 0x5F
Not applicable
R
No
Table 104. RANG_MDL Bit Definitions
Bits
Description
[15:3]
Not used
[3:2]
Gyroscope measurement range
00 = ±125°/sec (ADIS16505-1BMLZ)
01 = ±500°/sec (ADIS16505-2BMLZ)
10 = reserved
11 = ±2000°/sec (ADIS16505-3BMLZ)
[1:0]
Reserved, binary value = 11
Miscellaneous Control Register (MSC_CTRL)
Table 105. MSC_CTRL Register Definition
Addresses
Default
Access
Flash Backup
0x60, 0x61
0x00C1
R/W
Yes
Table 106. MSC_CTRL Bit Definitions
Bits
Description
[15:10]
Not used
9
BURST32. 32-bit burst enable bit. The user must wait
until a full data ready cycle until the burst array
updates with the desired data type. Changes to this bit
may take up to 200 μs after writing to indicate the new
value during readback.
1 = 32-bit burst data.
0 = 16-bit burst data (default).
8
BURST_SEL. Burst read output array selection. This bit
controls what calibrated data is in a burst read.
Changes to this bit may take up to 200 μs after writing
to indicate the new value during readback.
1 = burst data has delta angle and delta velocity data.
0 = burst data has gyroscope and accelerometer data
(default).
7
Linear acceleration compensation for gyroscopes.
When enabled, factory calibrated linear acceleration
compensation data is applied to the gyroscope
outputs. Changes to this bit may take up to 200 μs after
writing to indicate the new value during readback.
1 = enabled.
0 = disabled (default).
6
Point of percussion alignment. When set, this bit allows
for relocation of the acceleration sensors to a common
point of percussion on the package corner by
considering angular rotations. Changes to this bit may
take up to 200 μs after writing to indicate the new
value during readback.
1 = enabled.
0 = disabled (default).
5
Not used. Always set to 0.
4
SENS_BW. Internal sensor bandwidth. Changing this
bit reinitializes the sensors, and the user must wait
until the DR pin starts toggling after changing this bit.
This operation may require up to 250 ms to complete.
0 = wide bandwidth (default), see Table 1.
1 = 370 Hz. The gyroscope group delay increases by
0.17 ms and the accelerometer group delay increases
by 0.63 ms in this mode.
[3:2]
SYNC mode select (see the Clock Control section for
more information). The user must wait until the DR pin
starts toggling after changing these bits and/or the
UP_SCALE register in order to correctly read back the
new values. However, the user can write these registers
in succession before waiting for the DR pin to resume
toggling.
00 = internal SYNC (default). Internal 2 kHz clock used.
01 = direct input sync mode. The user provides an
external input clock between 1900 Hz and 2100 Hz.
10 = scaled sync mode. The user provides an external
input clock between 1 Hz and 128 Hz, which upscales
to 1900 Hz to 2100 Hz inside the ADIS16505.



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