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PSD813F2 bảng dữ liệu(PDF) 95 Page - STMicroelectronics

tên linh kiện PSD813F2
Giải thích chi tiết về linh kiện  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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PSD813F2 bảng dữ liệu(HTML) 95 Page - STMicroelectronics

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PSD8XX Family
PSD835G2
94
Microcontroller Interface – PSD835G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Symbol
Parameter
Min
Typ
Max
Unit
Flash Program
8.5
sec
Flash Bulk Erase (Preprogrammed to 00) (Note 1)
3
30
sec
Flash Bulk Erase
10
sec
tWHQV3
Sector Erase (Preprogrammed to 00)
1
30
sec
tWHQV2
Sector Erase
2.2
sec
tWHQV1
Word Program
14
1200
µs
Program/Erase Cycles (Per Sector)
100,000
cycles
tWHWLO
Sector Erase Time-Out
100
µs
tQ7VQV
DQ7 Valid to Output Valid (Data Polling)
30
ns
(Note 2)
Flash Program, Write and Erase Times (3.0 V to 3.6 V Versions)
-90
-12
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
tISCCF
TCK Clock Frequency (except for PLD)
(Note 1)
15
12
MHz
tISCCH
TCK Clock High Time
(Note 1)
30
40
ns
tISCCL
TCK Clock Low Time
(Note 1)
30
40
ns
tISCCF-P
TCK Clock Frequency (for PLD only)
(Note 2)
2
2
MHz
tISCCH-P
TCK Clock High Time (for PLD only)
(Note 2)
240
240
ns
tISCCL-P
TCK Clock Low Time (for PLD only)
(Note 2)
240
240
ns
tISCPSU
ISC Port Set Up Time
11
12
ns
tISCPH
ISC Port Hold Up Time
5
5
ns
tISCPCO
ISC Port Clock to Output
26
32
ns
tISCPZV
ISC Port High-Impedance to Valid Output
26
32
ns
tISCPVZ
ISC Port Valid Output to High-Impedance
26
32
ns
ISC Timing (3.0 V to 3.6 V Versions)
NOTES: 1. Programmed to all zeros before erase.
2. The polling status DQ7 is valid tQ7VQV ns before the data DQ0-7 is valid for reading.
NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode.
2. For program or erase PLD only.



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