PSD813F2 datasheet(94/110 Pages) STMICROELECTRONICS

tên linh kiện	PSD813F2

Giải thích chi tiết về linh kiện	Configurable Memory System on a Chip for 8-Bit Microcontrollers

PDF	110 Pages

Scroll/Zoom	100%

nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

Trang chủ	http://www.st.com

Logo

94 / 110 page

PSD835G2

PSD8XX Family

-90

-12

Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

tLVDV

ALE Access Time from

Power Down

128

135

Maximum Delay from APD Enable

tCLWH

to Internal PDN Valid Signal

Using CLKIN Input

15 * tCLCL (µs) (Note 1)

µs

Power Down Timing (3.0 V to 3.6 V Versions)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tNLNH

Warm RESET Active Low Time (Note 1)

300

tOPR

RESET High to Operational Device

300

tNLNH-PO

Power On Reset Active Low Time

Warm RESETActive Low Time

tNLNH-A

(Note 2)

µs

Reset Pin Timing (3.0 V to 3.6 V Versions)

NOTE: 1. tCLCL is the CLKIN clock period.

Microcontroller Interface – PSD835G2 AC/DC Parameters

(3.0 V to 3.6 V Versions)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tBVBH

Vstby Detection to Vstbyon Output

High

(Note 1)

µs

tBXBL

Vstby Off Detection to Vstbyon

Output Low

(Note 1)

µs

Vstbyon Timing (3.0 V to 3.6 V Versions)

NOTE: 1. RESET will not abort Flash programming/erase cycles.

2. RESET will abort Flash programming or erase cycle.

NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.

PSD813F2 bảng dữ liệu(PDF) 94 Page - STMicroelectronics

PSD813F2 bảng dữ liệu(HTML) 94 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL