RZSLASHN2L datasheet(6/128 Pages) RENESAS

6 / 128 page

Table 1.8

Communication interfaces (2 of 3)

Feature

Functional description

Ethernet switch (ETHSW)

● 3-port PHY interfaces

● IEEE802.3

● Support for 10/100/1000 Mbps data transfer

● Full and half duplex (1000 Mbps supports full-duplex only)

● Hardware switching, lookup, and filtering

● QoS with frame prioritization

● Priority control based on VLAN Priority (IEEE802.1q), which enables priority reassignment

● Classification and priority assignment based on IPv4 DiffServ Code Point Field, IPv6 Class

of Service

● Queue with eight priority levels

● Multicasting and broadcasting

● VLAN frame

● IEEE 1588-2008 compatible

● Programmable addition, removal and manipulation of ingress and egress VLAN tags,

supporting single and double-tagged VLAN frames on each port

● Cut-through and hub features

● Device level ring (DLR)

● Programmable egress rate limit per port

● Ingress Configurable Broadcast/multicast storm protection per port

● IEEE802.1X source address authentication supported

● IEEE802.1X guest VLAN supported

● PRP functionality (IEC 62439-3 edition 2.0- 2012)

● Configurable Time Multiplexed (TDMA) output queue scheduler supporting real-time

network infrastructures using time slots for bandwidth reservation enabling deterministic

delays

● Pattern matchers 12 channels

● Independent two timer module are available for timestamping and time for TDMA.

● Remote monitoring through SNMP

● Powerlink capable hub

● Ingress filtering and frame header manipulation (active stream identification, flow metering)

with Enhanced Frame Parser

● 4 additional PTP timer pulse generators

● MAC to MAC connection

● MII/RMII/RGMII interface is supported

EtherCAT slave controller (ESC)*1

● 1 channel (3 ports)

● EtherCAT Slave Controller IP core (made by Beckhoff Automation GmbH) implemented

● MII/RMII/RGMII interface is supported by external RGMII converter.

USB 2.0 HS host/function module

● 1 port

● Compliance with the USB 2.0 specification

● OTG support

● Transfer rate

High speed (480 Mbps), full speed (12 Mbps), low speed (1.5 Mbps, host only)

● Communications buffer

– Incorporates 1 KB of RAM for host mode

– Incorporates 8 KB of RAM for function mode

● DMAC (2 channels) incorporated

Serial communication interface (SCI)

● 6 channels

● 5 communication mode

– Asynchronous interfaces

– 8-bit clock synchronous interface

– Simple I2C (master-only)

– Simple SPI

– Smart card interface

● Clock source is select from among four internal clock signals

● Bit rate specifiable with the on-chip baud rate generator

● Full-duplex and half-duplex communication

● Data length: 7 to 9 bits (Asynchronous mode)

● Bit rate modulation

● Double speed mode

● Loopback function to enable self-diagnosis (Asynchronous, Clock synchronous mode)

I2C bus interface (IIC)

● 3 channels

● Communication formats: I2C bus format or SMBus format

● Master or slave mode selectable

● Supports the multi-master

● Maximum transfer rate: 400 kbps (Standard mode and Fast mode)

RZ/N2L Datasheet

1. Overview

R01DS0397EJ0140 Rev.1.40

Mar 31, 2026

Page 6 of 128

RZ/N2L bảng dữ liệu(PDF) 6 Page - Renesas Technology Corp

RZ/N2L bảng dữ liệu(HTML) 6 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL