RZSLASHN2L datasheet(5/128 Pages) RENESAS

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Table 1.7

Timers (2 of 2)

Feature

Functional description

Compare match timer (CMT)

● (16 bits × 2 channels) × 3 units

● Select from among four counter-input clock signals for each channel (with maximum

operating frequency of 50 MHz)

Compare match timer W (CMTW)

● (32 bits × 1 channel) × 2 units

● Compare-match, input-capture input, and output-comparison output are available.

● Select from among four counter-input clock signals for each channel (with maximum

operating frequency of 50 MHz)

● Interrupt requests can be output in response to compare-match, input-capture, and output-

comparison events.

Watchdog timer (WDT)

● 14 bits × 1 channel

● Select from among six counter-input clock signals for each channel (with maximum

operating frequency of 50 MHz)

Port output enable 3 (POE3)

● Control of the high-impedance state of the MTU3 waveform output pins

● 5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#

● Initiation on detection of short-circuited outputs (detection of simultaneous PWM output to

the active level)

● Initiation by input clock oscillation-stoppage detection, PLL oscillation anomaly detection,

DSMIF error detection, or software

● Additional programming of output control target pins is enabled

Port output enable for GPT (POEG)

● Controlling the output disable for GPT waveform output

● Initiation by input level detection of GTETRG pins

● Initiation by output disable request from GPT

● Initiation by detection of oscillation stop, DSMIF error, or by software

Real time clock (RTC)

● A 100 year calendar from 2000 to 2099

● BCD code display

● Clock source is division of main oscillator or PLL.

● Automatic adjustment function for leap years

Table 1.8

Communication interfaces (1 of 3)

Feature

Functional description

Ethernet MAC (GMAC)

● 1 port

● IEEE802.3

● IEEE1588-2008

● IEEE802.3-az-2010 for EEE

● 10BASE, 100BASE, and 1000BASE supported

● Full duplex and half duplex are supported

● Programmable frame length to support both standard and jumbo frames up to 16 KB

● 17 MAC address registers for the address filter block

● Variety of flexible addresses filtering modes are supported

● Advanced IEEE 1588-2002 & 2008 Ethernet frame time-stamping supported

● MII/RMII/RGMII interface is supported

RZ/N2L Datasheet

1. Overview

R01DS0397EJ0140 Rev.1.40

Mar 31, 2026

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