R7KA8D2AFDCAB datasheet(69/292 Pages) RENESAS

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Table 2.24

Current of high-speed mode, CPU Sleep mode (DCDC mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

Supply

current

*1*3*4

CPUCLK0 = 1

GHz

CPUCLK1 = 250

MHz

VSCR_1

ICC_DCDC*5

203

—

VCC_DCDC = 3.3 V

IDD*2

522

—

CPUCLK0 = 800

MHz

CPUCLK1 = 200

MHz

VSCR_1

ICC_DCDC*5

—

233

IDD*2

—

597

CPUCLK0 = 600

MHz

CPUCLK1 = 150

MHz

VSCR_2

ICC_DCDC*5

188

224

IDD*2

492

585

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. IDD depends on f (ICLK) as follows.

IDD Typ. = 0.02 × fCPUCLK0 + 0.06 × fICLK + 57 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 95℃) = 0.02 × fCPUCLK0 + 0.05 × fICLK + 490 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 105℃) = 0.02 × fCPUCLK0 + 0.05 × fICLK + 568 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 95℃) = 0.02 × fCPUCLK0 + 0.13 × fICLK + 477 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 105℃) = 0.02 × fCPUCLK0 + 0.13 × fICLK + 552 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 3. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 4. MRICLK, MRPCLK, ICLK, PCLKA, PCLKB, PCLKC, PCLKD, PCLKE and BCLK are set to divided by 64.

Note 5. Typical DCDC efficiency and the voltage of the test conditions are applied.

Table 2.25

Current of high-speed mode, CPU Sleep mode (External VDD mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

Supply

current

*1*3*4

CPUCLK0 = 1

GHz

CPUCLK1 = 250

MHz

VCL = voltage

range 1

IDD*2

522

—

CPUCLK0 = 800

MHz

CPUCLK1 = 200

MHz

VCL = voltage

range 1

IDD*2

—

597

CPUCLK0 = 600

MHz

CPUCLK1 = 150

MHz

VCL = voltage

range 2

IDD*2

492

585

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. IDD depends on f (ICLK) as follows.

IDD Typ. = 0.02 × fCPUCLK0 + 0.06 × fICLK + 57 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 1, 95℃) = 0.02 × fCPUCLK0 + 0.05 × fICLK + 490 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 1, 105℃) = 0.02 × fCPUCLK0 + 0.05 × fICLK + 568 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 2, 95℃) = 0.02 × fCPUCLK0 + 0.13 × fICLK + 477 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 2, 105℃) = 0.02 × fCPUCLK0 + 0.13 × fICLK + 552 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 3. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 4. MRICLK, MRPCLK, ICLK, PCLKA, PCLKB, PCLKC, PCLKD, PCLKE and BCLK are set to divided by 64.

RA8D2 Datasheet

2. Electrical Characteristics

R01DS0493EJ0130 Rev.1.30

Feb 27, 2026

Page 69 of 292

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