R7FA6T2AB3CFM datasheet(74/101 Pages) RENESAS

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tdr

Main clock

OSTDSR.OSTDF

MOCO clock

ICLK

Figure 2.54

Oscillation stop detection timing

2.10

POR and LVD Characteristics

Table 2.48

Power-on reset circuit and voltage detection circuit characteristics (1)

Parameter

Symbol Min

Typ

Max

Test conditions

Voltage detection

level

Power-on reset

(POR)

DPSBYCR.DEEPCUT[1:0] = 00b or

01b.

VPOR

2.5

2.6

2.7

Figure 2.55

DPSBYCR.DEEPCUT[1:0] = 11b.

1.8

2.25

2.7

Voltage detection circuit (LVD0)

Vdet0_1

2.84

2.94

3.04

Figure 2.56

Vdet0_2

2.77

2.87

2.97

Vdet0_3

2.70

2.80

2.90

Voltage detection circuit (LVD1)

Vdet1_1

2.89

2.99

3.09

Figure 2.57

Vdet1_2

2.82

2.92

3.02

Vdet1_3

2.75

2.85

2.95

Voltage detection circuit (LVD2)

Vdet2_1

2.89

2.99

3.09

Figure 2.58

Vdet2_2

2.82

2.92

3.02

Vdet2_3

2.75

2.85

2.95

Internal reset time Power-on reset time

tPOR

—

4.5

—

ms Figure 2.55

LVD0 reset time

tLVD0

—

0.51

—

Figure 2.56

LVD1 reset time

tLVD1

—

0.38

—

Figure 2.57

LVD2 reset time

tLVD2

—

0.38

—

Figure 2.58

Minimum VCC down time*1

tVOFF

200

—

µs

Figure 2.55,

Figure 2.56

Response delay

tdet

—

200

µs

Figure 2.56 to

Figure 2.58

LVD operation stabilization time (after LVD is enabled)

td(E-A)

—

µs

Figure 2.57,

Figure 2.58

Hysteresis width (LVD1 and LVD2)

VLVH

—

Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,

Vdet1, and Vdet2 for POR and LVD.

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0150 Rev.1.50

Jul 2, 2025

Page 74 of 101

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