R7FA6T2AB3CFM datasheet(50/101 Pages) RENESAS

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SDAn

SCLn

VIH

VIL

P*1

S*1

tSf

tSr

tSDAH

tSDAS

tSP

P*1

Test conditions:

VIH = VCC × 0.7, VIL = VCC × 0.3

VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0)

VOL = 0.4 V, IOL = 20 mA (ICFER.FMPE = 1)

Sr*1

Note:

n = 0 to 4, 9

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.38

SCI simple IIC mode timing

2.3.10

SPI Timing

Table 2.28

SPI timing (1 of 2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

High Speed/

Default

Symbol

VCC = 3.0 to 3.6 V, C = 15

VCC = 2.7 to 3.6 V, C = 30

Unit

Note

Min

Max

Min

Max

RSPCK clock cycle

Master

tSPcyc

4096

tTcyc

Slave

—

RSPCK clock high

pulse width

Master

tSPCKWH

(tSPcyc –

tSPCKr –

tSPCKf)/2 – 3

—

(tSPcyc –

tSPCKr –

tSPCKf)/2 – 3

—

Slave

0.4

0.6

0.4

0.6

tSPcy

RSPCK clock low

pulse width

Master

tSPCKWL

(tSPcyc –

tSPCKr –

tSPCKf)/2 – 3

—

(tSPcyc –

tSPCKr –

tSPCKf)/2 – 3

—

Slave

0.4

0.6

0.4

0.6

tSPcy

RSPCK clock rise

and fall time

Output

tSPCKr,

tSPCKf

—

Input

—

µs

Data input setup

time

Master

High

Speed*1

tSU

—

Default*2　

—

1.3

—

Slave

2.5

—

2.7

—

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0150 Rev.1.50

Jul 2, 2025

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