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R7FA6T2AB3CFM bảng dữ liệu(HTML) 59 Page - Renesas Technology Corp |
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59 / 101 page ![]() Table 2.32 IIC timing (2) Setting of the SCL0_A, SDA0_A pins are not required with the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Typ Max Unit Test conditions IIC (Hs-mode) BFCTL.HSME = 1 SCL input cycle time tSCL 10 (12) × tIICcyc + 80 — — ns Figure 2.48 SCL input high pulse width tSCLH 5 (6) × tIICcyc — — ns SCL input low pulse width tSCLL 5 (6) × tIICcyc — — ns SCL rise time Cb = 400pF tSrCL — — 80 ns Cb = 100pF — — 40 ns SDA rise time Cb = 400pF tSrDA — — 160 ns Cb = 100pF — — 80 ns SCL fall time Cb = 400pF tSfCL — — 80 ns Cb = 100pF — — 40 ns SDA fall time Cb = 400pF tSfDA — — 160 ns Cb = 100pF — — 80 ns SCL, SDA input spike pulse removal time tSP 0 — 1 (1) × tIICcyc ns START condition input hold time tSTAH tIICcyc + 40 — — ns Repeated START condition input setup time tSTAS 40 — — ns STOP condition input setup time tSTOS 40 — — ns Data input setup time tSDAS 10 — — ns Data input hold time Cb = 400pF tSDAH 0 — 150 ns Cb = 100pF 0 — 70 ns SCL, SDA capacitive load Cb*1 — — 400 pF SCL output minimum high pulse width Cb = 400pF tSCLH — 120 225 ns Cb = 100pF — 60 130 SCL output minimum low pulse width Cb = 400pF tSCLL — — 320 ns Cb = 100pF — — 160 Note: tIICcyc: IIC internal reference clock (IICφ) cycle. Note: Values in parentheses apply when INCTL.DNFS[3:0] is set to 0011b while the digital filter is enabled with INCTL.DNFE set to 1. Note: Targets are SCL0_A and SDA0_A. Note 1. Cb indicates the total capacity of the bus line. RA6T2 Datasheet 2. Electrical Characteristics R01DS0400EJ0150 Rev.1.50 Jul 2, 2025 Page 59 of 101 |
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