R7FA6T2AB3CFP datasheet(25/101 Pages) RENESAS

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Note 7. Reference value

Note 8. The DAC12 includes the Reference current in the analog power supply current.

Note 9. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (A/D Converter Module Stop bit) is in the module-stop

state.

Note 10. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.6 kHz).

Table 2.8

Coremark and normal mode current

Parameter

Symbol

Typ

Unit

Test conditions

Supply Current*1

Coremark

ICC

139

µA/MHz

ICLK = 240 MHz

PCLKA =

PCLKB =

PCLKC =

PCLKD =

FCLK =

3.75 MHz

Normal mode

All peripheral

clocks disabled,

cache on,

while (1) code

executing from

flash*2

139

All peripheral

clocks disabled,

cache off,

while (1) code

executing from

flash*2

115

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

2.2.6

VCC Rise and Fall Gradient and Ripple Frequency

Table 2.9

VCC rise and fall gradient characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

VCC rising gradient

Voltage monitor 0 reset disabled at startup

SrVCC

0.0084 —

ms/V

—

Voltage monitor 0 reset enabled at startup

0.0084 —

—

SCI boot mode*1

0.0084 —

—

VCC falling gradient

SfVCC

0.0084 —

—

ms/V

—

Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit.

Table 2.10

VCC rising and falling gradient and ripple frequency characteristics

The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit (2.7

V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Allowable ripple

frequency

fr (VCC)

—

kHz

Figure 2.2

Vr (VCC) ≤ VCC × 0.2

—

MHz

Figure 2.2

Vr (VCC) ≤ VCC × 0.08

—

MHz

Figure 2.2

Vr (VCC) ≤ VCC × 0.06

Allowable voltage

change rising and

falling gradient

dt/dVCC

1.0

—

ms/V

When VCC change

exceeds VCC ±10%

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0150 Rev.1.50

Jul 2, 2025

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