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R7FA6T2AB3CFP bảng dữ liệu(HTML) 51 Page - Renesas Technology Corp |
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51 / 101 page  Table 2.28 SPI timing (2 of 2) Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter High Speed/ Default Symbol VCC = 3.0 to 3.6 V, C = 15 pF VCC = 2.7 to 3.6 V, C = 30 pF Unit Note Min Max Min Max Data input hold time Master High Speed*1 tH 6.2 — — — ns Default*2 — — 8 — ns Slave 2.5 — 2.5 — ns SSL setup time Master tLEAD 1 8 1 8 tSPcy c Slave 6 — 6 — tTcyc SSL hold time Master tLAG 1 8 1 8 tSPcy c Slave 6 — 6 — tTcyc TI SSP SS input setup time Slave tTISS 2.5 — 2.8 — ns TI SSP SS input hold time Slave tTISH 2.5 — 2.5 — ns TI SSP next-access time Slave tTIND 2 × tTcyc + SLNDL × tTcyc — 2 × tTcyc + SLNDL × tTcyc — ns TI SSP master SS output delay Master tTISSOD — 8.9 — 8.9 ns Data output delay time Master High Speed*1 tOD — 4.6 — — ns Default*2 — — — 7 ns Slave High Speed*1 — 14 — — ns Default*2 — — — 21 ns Data output hold time Master tOH 0 — 0 — ns Slave 0 — 0 — ns Successive transmission delay time Master tTD tSPcyc + 2 × tTcyc 8 × tSPcyc + 2 × tPcyc tSPcyc + 2 × tTcyc 8 × tSPcyc + 2 × tPcyc ns Slave tTcyc — tTcyc — ns MOSI and MISO rise and fall time Output tDr — 5 — 5 ns Input tDf — 1 — 1 µs SSL rise and fall time Output tSSLr — 5 — 5 ns Input tSSLf — 1 — 1 µs Slave access time Slave tSA — 20 — 20 ns Slave output release time Slave tREL — 20 — 20 ns Note: tTcyc: PCLKA or SCISPICLK cycle. Note 1. Must use pins that have a letter appended to their name, for instance _A, _B, _C, to indicate group membership. SPIA is instance _B, SPIB is instance _A. Note 2. All pins of group membership can be used. RA6T2 Datasheet 2. Electrical Characteristics R01DS0400EJ0150 Rev.1.50 Jul 2, 2025 Page 51 of 101 |
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