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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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R7FA6T2AB3CFP bảng dữ liệu(PDF) 61 Page - Renesas Technology Corp |
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R7FA6T2AB3CFP bảng dữ liệu(HTML) 61 Page - Renesas Technology Corp |
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61 / 101 page  2.4 A/D Converter Characteristics Table 2.34 A/D conversion characteristics (Common) Parameter Min Typ Max Unit Test condi tions A/D conversion clock frequency(ADCLK) 25 50 60 MHz — Successive approximation time 100 — 140 ns — A/D sampling time Self-calibration SAR mode 1 × tADcyc + 40 — — ns — Oversampling mode 1 × tADcyc + 40 — — ns — Hybrid mode 1 × tADcyc + 60 — — ns — Self-diagnosis SAR mode 1 × tADcyc + 40 — — ns — Oversampling mode 1 × tADcyc + 40 — — ns — Hybrid mode 1 × tADcyc + 60 — — ns — A/D conversion High- precision high- speed channels Without channel- dedicated sample- and-hold circuits (AN000 to AN005) (AN006 to AN011) (AN018 to AN019) SAR mode 1 × tADcyc + 40 — — ns — Oversampling mode 1 × tADcyc + 40 — — ns — Hybrid mode 1 × tADcyc + 60 — — ns — With channel- dedicated sample- and-hold circuits (AN000 to AN005) (AN006 to AN011) SAR mode 1 × tADcyc + 160 — — ns — Hybrid mode 1 × tADcyc + 160 — — ns — High-precision middle- speed channels (AN012 to AN017) SAR mode 180 — — ns — Oversampling mode 180 — — ns — Hybrid mode 180 — — ns — Normal-precision low- speed channels (AN020 to AN028) SAR mode 400 — — ns — Oversampling mode 400 — — ns — Hybrid mode 400 — — ns — Channel- dedicated sample- and-hold circuits Sampling time Self-calibration 1 × tADcyc + 400 — — ns — A/D conversion 400 — — ns — Hold mode switching time 40 — — ns — Hold time — — 5 µs — Operation stabilization time A/D start-up time 2.0 — — µs — Channel-dedicated sample-and-hold circuits start-up time 2.0 — — µs — A/D shut-down time 1.0 — — µs — Note: tADcyc : ADCLK cycle RA6T2 Datasheet 2. Electrical Characteristics R01DS0400EJ0150 Rev.1.50 Jul 2, 2025 Page 61 of 101 |
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