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R7FA6T2AB3CFP bảng dữ liệu(PDF) 92 Page - Renesas Technology Corp |
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R7FA6T2AB3CFP bảng dữ liệu(HTML) 92 Page - Renesas Technology Corp |
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92 / 101 page ![]() Appendix 3. I/O Registers This appendix describes I/O register address and access cycles by function. 3.1 Peripheral Base Addresses This section provides the base addresses for peripherals described in this manual. Table A3.1 shows the name, description, and the base address of each peripheral. Table A3.1 Peripheral base address (1 of 3) Name Description Base address RMPU Renesas Memory Protection Unit 0x4000_0000 TZF TrustZone Filter 0x4000_0E00 SRAM SRAM Control 0x4000_2000 BUS BUS Control 0x4000_3000 DMAC0 Direct memory access controller 0 0x4000_5000 DMAC1 Direct memory access controller 1 0x4000_5040 DMAC2 Direct memory access controller 2 0x4000_5080 DMAC3 Direct memory access controller 3 0x4000_50C0 DMAC4 Direct memory access controller 4 0x4000_5100 DMAC5 Direct memory access controller 5 0x4000_5140 DMAC6 Direct memory access controller 6 0x4000_5180 DMAC7 Direct memory access controller 7 0x4000_51C0 DMA DMAC Module Activation 0x4000_5200 DTC Data Transfer Controller 0x4000_5400 ICU Interrupt Controller 0x4000_6000 CACHE CACHE 0x4000_7000 CPSCU CPU System Security Control Unit 0x4000_8000 DBG Debug Function 0x4001_B000 FCACHE Flash Cache 0x4001_C100 SYSC System Control 0x4001_E000 PORT0 Port 0 Control Registers 0x4001_F000 PORT2 Port 2 Control Registers 0x4001_F040 PORTA Port A Control Registers 0x4001_F140 PORTB Port B Control Registers 0x4001_F160 PORTC Port C Control Registers 0x4001_F180 PORTD Port D Control Registers 0x4001_F1A0 PORTE Port E Control Registers 0x4001_F1C0 PFS_B Pmn Pin Function Control Register 0x4001_F800 IIRFA IIR Filter Accelerator 0x4002_0000 TFU Trigonometric Function Unit 0x4002_1000 ELC_B Event Link Controller 0x4008_2000 IWDT Independent Watchdog Timer 0x4008_3200 WDT Watchdog Timer 0x4008_3400 CAC Clock Frequency Accuracy Measurement Circuit 0x4008_3600 MSTP Module Stop Control A, B, C, D, E 0x4008_4000 RA6T2 Datasheet Appendix 3. I/O Registers R01DS0400EJ0150 Rev.1.50 Jul 2, 2025 Page 92 of 101 |
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