R7FA6T2AB3CFP datasheet(58/101 Pages) RENESAS

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Table 2.31

IIC timing (1)-3

Setting of the SCL0_A, SDA0_A pins are not required with the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

IIC

(Fast-mode+)

BFCTL.FMPE = 1

SCL input cycle time

tSCL

10 (18) × tIICcyc +

240

—

Figure 2.47

SCL input high pulse width

tSCLH

5 (9) × tIICcyc

—

SCL input low pulse width

tSCLL

5 (9) × tIICcyc

—

SCL, SDA rise time

tSr

—

120

SCL, SDA fall time

tSf

—

120

SCL, SDA input spike pulse

removal time

tSP

1 (4) × tIICcyc

SDA input bus free time

tBUF

5 (9) × tIICcyc + 120 —

START condition input hold time

tSTAH

tIICcyc + 120

—

Repeated START condition input

setup time

tSTAS

120

—

STOP condition input setup time

tSTOS

120

—

Data input setup time

tSDAS

tIICcyc + 30

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*1

—

550

Note:

tIICcyc: IIC internal reference clock (IICφ) cycle.

Note:

Values in parentheses apply when INCTL.DNFS[3:0] is set to 0011b while the digital filter is enabled with INCTL.DNFE set to 1.

Note:

Targets are SCL0_A and SDA0_A.

Note 1. Cb indicates the total capacity of the bus line.

SDAn

SCLn

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

S*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Sr*1

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.47

I2C bus interface input/output timing

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0150 Rev.1.50

Jul 2, 2025

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