STA333W datasheet(26/42 Pages) STMICROELECTRONICS

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STA333W

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DDX compensation pulse size register

Over-current warning detect adjustment bypass

The OCWARN input is used to indicate an over current warning condition. When OCWARN

is asserted (set to 0), the power control block will force an adjustment to the modulation limit

(default -3dB) in an attempt to eliminate the over-current warning condition. Once the

over-current warning volume adjustment is applied, it remains in this state until reset is

applied. The level of adjustment can be changed via the TWOCL (thermal warning/over

current limit) setting which is address 0x37 of the user defined coefficient RAM.

7.1.5

Configuration register D (address 0x03)

Zero-detect mute enable

Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at

the data for each processing channel at the output of the crossover (bass management)

Table 22.

DDX compensating pulse size

Bit

R/W

RST

Name

Description

2R/W

1CSZ0

When OM[1:0]: 11, this register determines the size of

the DDX compensating pulse from 0 to 15 clock periods.

3R/W

0CSZ1

4R/W

1CSZ2

5R/W

0CSZ3

Table 23.

Compensating pulse size

CSZ(3..0)

Compensating pulse size

0000

0 ns (0 ticks) compensating pulse size

0001

20 ns (1 tick) clock period compensating pulse size

……

1111

300 ns (15 ticks) clock period compensating pulse size

Table 24.

Over current warning detect adjustment bypass

Bit

R/W

RST

Name

Description

7R/W

1OCRB

0: over current warning adjustment enabled

1: over current warning adjustment disabled

MME

ZDE

XXXXXX

Table 25.

Zero detect mute enable

Bit

R/W

RST

Name

Description

R/W

ZDE

Setting of 1 enables the automatic zero-detect mute

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