STA333W datasheet(25/42 Pages) STMICROELECTRONICS

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STA333W

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Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

channel input mapping registers. This allows for flexibility in processing. The default settings

of these registers map each I2S input channel to its corresponding processing channel.

7.1.4

Configuration register C (address 0x02)

DDX power output mode

The DDX power output mode selects how the DDX output timing is configured. Different

power devices use different output modes. The STA50x or STA51x recommended use is

OM = 10.

Table 19.

Channel input mapping

Bit

R/W

RST

Name

Description

6R/W

0C1IM

0: processing channel 1 receives left I2S input

1 : processing channel 1 receives right I2S input

7R/W

0C2IM

0: processing channel 2 receives left I2S input

1: processing channel 2 receives right I2S input

OCRB

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

Table 20.

DDX power output mode

Bit

R/W

RST

Name

Description

0R/W

1OM0

The DDX power output mode selects configuration of

DDX output.

1R/W

1OM1

Table 21.

Output modes

OM[1:0]

Output stage – mode

STA50x: drop compensation

Discrete output stage: tapered compensation

STA50x: full power mode

Variable drop compensation (CSZx bits)

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