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ZIOL2201 bảng dữ liệu(PDF) 62 Page - Renesas Technology Corp

tên linh kiện ZIOL2201
Giải thích chi tiết về linh kiện  IO-Link Compliant HV Line Driver IC Family
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ZIOL2201 bảng dữ liệu(HTML) 62 Page - Renesas Technology Corp

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ZIOL2xxx Datasheet
© 2016 Integrated Device Technology, Inc.
62
April 26, 2016
Figure 4.3
Power Line Fail Detection
ZIOL2401
AUX_EN
AUX_TX
WURQ
RX
TX
TX_EN
INT_L
RST_L
PFD
SW
FB
VDD
COM_O
VSS
LR_IN
LR_OUT
COM_I
AUX_O
Standard
Cable
Device (Sensor)
L1
R1
R2
C1
C3
C5
D1
C4
D2
D3
D6
D5
Vout
DC_RDY
L+
L-
C/Q
D7
D4
AUX_I
AUX_RX
C2
R4
R3
IMPORTANT:
R3 and R4 which perform
the line voltage sensor
shall connected directly to
the cable (L+/L-).
They must not be
connected to VDD/VSS!
The PCB layout design requires considering several recommendations. In particular the placement of decoupling
capacitors and the placement external components that perform the DC/DC converter circuits shall be done
carefully. Recommendations are:
•
Low resistive and low inductive ground interconnections due to metal ground areas surrounding the IC
or/and using a special “Ground” PCB layer.
•
The wiring of the channel driver output shall consider that the wires are designed for currents up to
500mA (depending on the IC configuration) and in combination with that wiring for VDD and VSS shall
designed for currents up to 1A.
•
Decoupling capacitors related to the IC pins VDD and LR_OUT (and LR_IN if applicable) shall placed
as close as possible to the IC pin.
•
The DC/DC converter requires an external Schottky-diode as free-wheel diode. Its anode shall be
interconnected to the SW pin. It is important that its cathode has good (short) ground connection. With
respect to all to the SW pin interconnected devices (free-wheel diode and inductor L1) all wires have to
be kept as short as possible. Moreover, the PCB design shall make sure that the parasitic coupling
between the node belonging to the SW pin and the node belonging to the FB pin of the IC is
minimized.
•
The voltage divider R1/R2 shall interconnected to the FB (feedback pin) in that way that the
electromagnetic coupling to the wire interconnected to the SW pin is low as possible.



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